The maximum bit error rate test range for external MUX/DEMUX is 56 Gbit/s

High quality (12 ps rise/fall time) and low jitter (8 ps p-p) PPG waveform, * high 3.5 vP-P

Ultra sensitive error code analyzer (typical value: 10 mV)

External MP1825B 32.1 Gbit/s fourth-order weighting

Synchronous parallel bit error rate and crosstalk detection, * 32 more channels

Shake tolerance test * high 32.1 Gbit/s

SJ * high 2000 UI. High modulation frequency SJ, up to 1 UI at 250 MHz

Double SJ, RJ, BUJ, SSC

Half periodic jitter (even/odd jitter)

PON burst signal detection and EDFA loop test

Flexible extensible plug-in module design

32.1 Gbaud 4PAM/8PAM generator and 4PAM error rate for accurate measurement

1 Tbit/s Next-generation high-speed transmission test (32G x 32CH)

Passive equalizer

The signal quality analyzer MP1800A is a highly extensible plug-in, modular bit error rate tester (BERT). It integrates the pulse code generator (PPG) module, which can generate the highest quality and largest amplitude signal in the industry, and integrates the error code analyzer (ED) module with the highest input sensitivity. The platform supports signal analysis including burst pattern, bath shake and eye map measurement. Various types of jitter, such as SJ, RJ, BUJ, SSC, etc., can be generated using the built-in jitter modulation source that supports device jitter tolerance testing.

The MP1800A BERT supports a wide range of bit rates from 0.1 to 32.1 Gbit/s, suitable for signal integrity analysis in a variety of applications, For example, 100 GbE (25Gx4), OTU-4 (28Gx4), 32G DP-QPSK, CEI-28G, 32G FC, Infiniband EDR (26G), and so on. In addition, the MP1800A, combined with MP1821A MUX and MP1822A DEMUX, supports up to 56 Gbit/s bit error rate (BER) testing, making it easy to upgrade for the development of next-generation applications such as CEI-56G-VSR.

The number of channels for each MP1800A series PPG or ED module can be selected from 1ch, 2ch, or 4ch. Multi-channel synchronization of up to 8 channels can be supported at 32 Gbit/s. Therefore, each channel of AOC, CFP, CXP, QSFP+ and so on can be measured simultaneously, realizing crosstalk and chattering tolerance evaluation tests.

The PPG module of SQA can output signals up to 3.5 VP-P, supporting the evaluation of EA and EML modulators. In addition to generating IEEE and ITU-T burst and auxiliary signals to evaluate E-PON, G-PON and 10G-PON optical modules, the burst data and auxiliary signals generated by SQA can be automatically set to output timing, thus shortening evaluation time and improving evaluation quality.

The ED module has a high sensitivity of 10 mV, as well as high-speed automatic adjustment of 1 second or less (automatic detection of threshold levels and phase points), supporting accurate, efficient measurements of low output amplitude devices, such as AOC. Installing clock recovery options helps SERDES with different Tx and Rx clocks to implement pressure chattering tolerance testing and BER measurements for clock-free devices such as AOC within a single module.

J1621A and J1622A are passive linear equalizers that can be used to help compensate for the effects caused by distortion of high frequency transmission lines. They can be connected to the ED to compensate for PCB track losses and improve eye-map opening. When combined with the highly sensitive ED MU183040B/MU183041B, these equalizers enable BER and chattering tolerance tests on PHY devices with low eye-map opening.

The jitter modulator can generate wide amplitude SJ of * 1 UI at 250 MHz jitter frequency to ensure sufficient margin for the chattering tolerance test of the receiver. In addition, it achieves ultra-low 275 fs RMS (rated) inherent jitter when jitter modulation is OFF or 0 UI is set to Jitter ON, ensuring accurate measurements even at low jitter amplitudes. In addition to supporting RJ, BUJ, SSC and dual-tone SJ, it also supports new standards such as CEI-28G and 100 GbE. The MP1800A from Anritsu is equipped with low inherent jitter PPG, fourth order weighting, high sensitivity ED, eye-map opening compensation equalizer, and automatic measurement software, making it an ideal overall solution for jiggle tolerance testing.

The MP1800A, combined with the fourth-order weighted MP1825B, generates the 32.1 Gbit/s pre-weighting required by high-speed interconnection standards, such as CEI-28G, 32G FC, and Infiniband EDR (26G). Because each stage can be changed separately, accurate pre-weighting is always ensured. The fourth order weighting MP1825B instrument as MP1800A remote rf head, and as close as possible to DUT placed, can minimize the impact of signal attenuation caused by cable loss and ISI, so as to ensure the highest signal quality at the DUT interface.

With the 4 PAM/8 PAM converter MZ1834A/MZ183, the 8AMP1800A can be configured to generate high-quality, low S/N 4 PAM and 8 PAM data signals required for features such as high-speed backplanes and 400 GbE interfaces. The ber of three 4 PAM eyes can be measured simultaneously. The MP1800A is an ideal platform for accurately measuring the bit error rate of 4PAM signals, using the long term storage programmable code type function and error masking to filter out unwanted errors.